1. Field of the Invention
The present invention relates to a method and related apparatus for reducing power consumption, and more particularly, to a method and related apparatus for reducing chipset power consumption while accessing memory modules.
2. Description of the Prior Art
Computer systems are indispensable to the information society. With the computer system, it is convenient for users to calculate, access, and manage a large amount of information, data, and video at high speed. Therefore, information technology manufacturers have been devoted to improving the performance of computer systems to manage data more securely and speedily. However, while the performance of computer systems is improved, how to reduce power consumption becomes an important issue.
Generally, a typical computer system comprises a central processing unit (CPU), a chipset, a memory device, and other peripheral circuits. The CPU can process information and data to control the operation of the computer system. The memory device, such as a dynamic random-access memory (DRAM), can temporarily store programs, and data required by the CPU. The chipset can manage the communication between the CPU (or other peripheral circuits) and the memory device.
Data is stored in the memory device and has a corresponding address that allows random access. In the computer system, the memory device includes several memory modules. Each memory module has a plurality of address pins, each address pin being used for receiving a one-bit address. The chipset includes a plurality of driving units respectively connected to the address pins of each memory module, each driving receiving power and outputting a one-bit address to a corresponding address pin. When the chipset accesses data of a certain address in the memory device, the chipset will control the driving units respectively to output a one-bit address to the corresponding address pins. Then the memory module gathers all one-bit addresses to obtain a complete address, such as a row address (RAS) or a column address (CAS). According to the assigned address, the chipset can access the required data.
In the prior art, memory modules are independent circuits and combined into a memory device, which is electrically connected to the computer system by insertion into a slot. Depending on the user's budget and requirement, the user can install the required memory capacity. As known in the art, a larger memory capacity requires more bits to assign addresses. Generally, driving units of the chipset are more than address pins of the memory device so as to support different memory capacities or larger memory capacities. For instance, most chipsets can support a 4 GB memory capacity. However, most memory device configurations have a memory capacity smaller than 4 GB and thereby require fewer address bits.
Current chipsets can support the configuration for 2-bit bank addresses and 14-bit RAS/CAS addresses, and therefore the typical chipset includes 16 driving units. Actually, it is only necessary to have 2-bit bank addresses and 12-bit RAS/CAS addresses to assign an address in a 64 MB memory module. However, in the prior art, no matter whether the configuration of the memory module is smaller than the memory capacity supported by the chipset, each driving unit of the chipset still consumes power. Thus, when the prior art computer system accesses the memory device, some address pins of the memory module are not used, but the corresponding driving units still consume power increasing overall power consumption.